Alif Semiconductor /AE722F80F55D5LS_CM55_HE_View /SDMMC /SDMMC_EMMC_CTRL_R

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Interpret as SDMMC_EMMC_CTRL_R

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)CARD_IS_EMMC 0 (Val_0x0)DISABLE_DATA_CRC_CHK 0 (Val_0x0)EMMC_RST_N 0 (Val_0x0)EMMC_RST_N_OE

DISABLE_DATA_CRC_CHK=Val_0x0, CARD_IS_EMMC=Val_0x0, EMMC_RST_N_OE=Val_0x0, EMMC_RST_N=Val_0x0

Description

eMMC Control Register

Fields

CARD_IS_EMMC

eMMC Card Present. This bit indicates the type of card connected. An application program this bit based on the card connected to the SDMMC Host Controller.

0 (Val_0x0): Card connected to the SDMMC Host Controller is a non-eMMC card

1 (Val_0x1): Card connected to the SDMMC Host Controller is an eMMC card

DISABLE_DATA_CRC_CHK

Disable Data CRC Check. This bit controls masking of CRC16 error for Card Write in eMMC mode. This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, which may generate CRC error. This CRC error can be masked using this bit during bus testing.

0 (Val_0x0): DATA CRC check is enabled

1 (Val_0x1): DATA CRC check is disabled

EMMC_RST_N

eMMC Device Reset Signal Control. This register field controls SD_RST output of the SDMMC module.

0 (Val_0x0): Reset to eMMC device asserted (active low)

1 (Val_0x1): Reset to eMMC device is de-asserted

EMMC_RST_N_OE

Output Enable Control for eMMC Device Reset Signal PAD Control. This field drives SD_RST output of the SDMMC module.

0 (Val_0x0): SD_RST is 0x0

1 (Val_0x1): SD_RST is 0x1

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